var searchData=
[
  ['variable_0',['Setup the PATH environment variable',['../page_build_guide.html#path_env',1,'']]],
  ['various_20api_20interfaces_1',['Various API interfaces',['../page_coding.html#coding_api',1,'']]],
  ['vco_2',['VCO',['../page_usrp_b100.html#b100_mcr_vco',1,'Set other rates - uses internal VCO'],['../page_usrp_e1x0.html#e1x0_intvco',1,'Set other rates - uses internal VCO']]],
  ['vcxo_3',['VCXO',['../page_usrp_b100.html#b100_mcr_vcxo',1,'Set 61.44 MHz - uses external VCXO'],['../page_usrp_e1x0.html#e1x0_mcr_extvcxo',1,'Set 61.44MHz - uses external VCXO']]],
  ['verification_4',['Verification',['../page_rdtesting.html#rdtesting_fpgadspverif',1,'FPGA DSP Verification'],['../page_rdtesting.html#rdtesting_fpgafuncverif',1,'FPGA Functional Verification']]],
  ['verification_3a_20automatic_20test_20procedure_5',['Verification: Automatic Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_auto',1,'FPGA DSP Verification: Automatic Test Procedure'],['../page_rdtesting.html#rdtesting_fpgafuncverif_auto',1,'FPGA Functional Verification: Automatic Test Procedure']]],
  ['verification_3a_20manual_20test_20procedure_6',['Verification: Manual Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_manual',1,'FPGA DSP Verification: Manual Test Procedure'],['../page_rdtesting.html#rdtesting_fpgafuncverif_manual',1,'FPGA Functional Verification: Manual Test Procedure']]],
  ['verify_20the_20contents_20of_20your_20kit_7',['Verify the Contents of Your Kit',['../page_usrp_b200.html#verify_contents',1,'']]],
  ['verify_20the_20operation_20of_20the_20usrp_8',['Test and Verify the Operation of the USRP',['../page_usrp_b200.html#verify_device_operation',1,'']]],
  ['version_9',['Kernel Version',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_kernel',1,'']]],
  ['version_20of_20the_20compat_20number_20supported_10',['Why is only one version of the compat number supported?',['../page_compat.html#compat_faq_why1',1,'']]],
  ['version_20of_20vivado_11',['Upgrade IP to the environment version of Vivado',['../md_usrp3_2vivado__env__utils.html#autotoc_md247',1,'']]],
  ['versioning_12',['UHD Semantic Versioning',['../page_semver.html',1,'page_uhd']]],
  ['vh_13',['vh',['../md_usrp3_2sim_2libs__axi.html#autotoc_md154',1,'AXI4 Stream (sim_axis_lib.vh)'],['../md_usrp3_2sim_2libs__general.html#autotoc_md193',1,'Clocks and Resets (sim_clks_rsts.vh)'],['../md_usrp3_2sim_2libs__axi.html#autotoc_md164',1,'Compressed VITA (sim_chdr_lib.vh)'],['../md_usrp3_2sim_2libs__general.html#autotoc_md186',1,'Execution and Reporting (sim_exec_report.vh)'],['../md_usrp3_2sim_2libs__axi.html#autotoc_md178',1,'Memory Mapped AXI4 (sim_axi4_lib.vh)']]],
  ['via_20command_20line_14',['Device discovery via command line',['../page_identification.html#id_identifying_cmdline',1,'']]],
  ['via_20ethernet_15',['Uploading the firmware via Ethernet',['../page_octoclock.html#firmware',1,'']]],
  ['via_20macports_16',['Via MacPorts',['../page_install.html#install_osx_macports',1,'']]],
  ['via_20name_17',['Discovery via name',['../page_identification.html#id_naming_discovery',1,'']]],
  ['visa_20scpi_20based_20devices_18',['VISA/SCPI based devices',['../page_power.html#power_usercal_extend_visa',1,'']]],
  ['visual_20studio_19',['Build the project in Visual Studio',['../page_build_guide.html#build_in_msvc',1,'']]],
  ['vita_20sim_5fchdr_5flib_20vh_20',['Compressed VITA (sim_chdr_lib.vh)',['../md_usrp3_2sim_2libs__axi.html#autotoc_md164',1,'']]],
  ['vivado_21',['Vivado',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md209',1,'Simulating with ModelSim through Vivado'],['../md_usrp3_2vivado__env__utils.html#autotoc_md247',1,'Upgrade IP to the environment version of Vivado']]],
  ['vivado_202021_201_22',['Vivado 2021 1',['../md_usrp3_2build__instructions.html#autotoc_md121',1,'Error During cs_server Initialization in Vivado 2021.1'],['../md_usrp3_2build__instructions.html#autotoc_md120',1,'N2rt13HDRTExceptionE in Vivado 2021.1']]],
  ['vivado_20block_20design_20bd_23',['Modify existing Vivado Block Design (BD)',['../md_usrp3_2vivado__env__utils.html#autotoc_md244',1,'']]],
  ['vivado_20environment_20utilities_24',['Vivado Environment Utilities',['../md_usrp3_2vivado__env__utils.html',1,'']]],
  ['vivado_20hardware_20console_25',['Launch Vivado Hardware Console',['../md_usrp3_2vivado__env__utils.html#autotoc_md249',1,'']]],
  ['vivado_20ip_26',['Vivado IP',['../md_usrp3_2vivado__env__utils.html#autotoc_md242',1,'Create Vivado IP'],['../md_usrp3_2vivado__env__utils.html#autotoc_md246',1,'List supported Vivado IP'],['../md_usrp3_2vivado__env__utils.html#autotoc_md243',1,'Modify existing Vivado IP']]],
  ['vivado_20make_20options_27',['Xilinx Vivado Make Options',['../md_usrp3_2build__instructions.html#autotoc_md147',1,'']]],
  ['vivado_20not_20found_28',['Vivado Not Found',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md214',1,'']]],
  ['vivado_20only_29',['Build Instructions (Xilinx Vivado only)',['../md_usrp3_2build__instructions.html#autotoc_md116',1,'']]],
  ['vivado_20tcl_20based_20block_20design_30',['Modify existing Vivado Tcl-based Block Design',['../md_usrp3_2vivado__env__utils.html#autotoc_md245',1,'']]],
  ['vivado_20xsim_31',['Using Xilinx Vivado XSim',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md206',1,'']]],
  ['volatility_32',['Certificate of Volatility',['../page_usrp_b200.html#b200_letter_of_volatility',1,'']]],
  ['volk_33',['Compiling GNURadio with Volk',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_volk_volk',1,'']]],
  ['voltage_34',['Configuring GPIO Voltage',['../page_x400_gpio_api.html#x4x0_gpio_voltage',1,'']]],
  ['vrt_35',['VRT',['../page_rtp.html#rtp_vrt',1,'']]],
  ['vs_20embedded_20mode_36',['Network vs. Embedded Mode',['../page_mpm.html#mpm_modes',1,'']]],
  ['vs_20rx_20tuning_37',['Sign of DSP frequency on TX vs. RX tuning',['../page_general.html#general_tuning_dsp_sign',1,'']]]
];
