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  ['the_20dependencies_20on_20ubuntu_47',['Setting up the dependencies on Ubuntu',['../page_build_guide.html#build_dependencies_ubuntu',1,'']]],
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  ['the_20file_20system_62',['Updating the file system',['../page_usrp_e3xx.html#e3xx_getting_started_fs_update',1,'']]],
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  ['the_20pci_20express_20card_98',['Installing the PCI Express Card',['../page_usrp_x3x0.html#autotoc_md67',1,'']]],
  ['the_20pci_20express_20interface_20kit_99',['Installing the PCI Express Interface Kit',['../page_usrp_x3x0.html#autotoc_md63',1,'']]],
  ['the_20pcie_20kernel_20drivers_100',['the PCIe Kernel Drivers',['../page_usrp_x3x0.html#autotoc_md62',1,'Installing the PCIe Kernel Drivers'],['../page_usrp_x3x0.html#autotoc_md66',1,'Installing the PCIe Kernel Drivers']]],
  ['the_20project_20in_20msvc_20command_20line_101',['Build the project in MSVC (command line)',['../page_build_guide.html#build_msvc_cmd_line',1,'']]],
  ['the_20project_20in_20visual_20studio_102',['Build the project in Visual Studio',['../page_build_guide.html#build_in_msvc',1,'']]],
  ['the_20project_20with_20cmake_103',['Generate the project with CMake',['../page_build_guide.html#cmake_win',1,'']]],
  ['the_20python_20api_104',['the Python API',['../page_python.html#python_install',1,'Installing the Python API'],['../page_python.html#python_usage',1,'Using the Python API']]],
  ['the_20python_20global_20interpreter_20lock_105',['Thread Safety and the Python Global Interpreter Lock',['../page_python.html#python_usage_gil',1,'']]],
  ['the_20receive_20chain_3a_106',['Tuning the receive chain:',['../page_general.html#general_tuning_rxchain',1,'']]],
  ['the_20resolve_20method_20in_20a_20subclass_107',['is required to implement the &quot;resolve&quot; method in a subclass.',['../classuhd_1_1experts_1_1worker__node__t.html#autotoc_md259',1,'']]],
  ['the_20rfnoc_20api_108',['High-Level: The RFNoC API',['../page_coding.html#coding_api_hilevel_rfnoc',1,'']]],
  ['the_20sd_20card_109',['The SD card',['../page_usrp_e3xx.html#e3xx_sdcard',1,'']]],
  ['the_20sd_20card_110',['Updating the SD card',['../page_usrp_e3xx.html#update_sdcard',1,'']]],
  ['the_20sd_20card_20usrp2_20only_111',['Load the Images onto the SD card (USRP2 only)',['../page_usrp2.html#usrp2_load',1,'']]],
  ['the_20sensor_20api_112',['The sensor API',['../page_usrp_e3xx.html#e3xx_usage_sensors',1,'']]],
  ['the_20serial_20output_113',['Monitor the serial output',['../page_usrp2.html#usrp2_commprob_uart',1,'']]],
  ['the_20signal_20chain_20in_20generation_202_20products_114',['Customizing the Signal Chain in Generation 2 products',['../md_usrp2_2customize__signal__chain.html',1,'']]],
  ['the_20simulation_20with_20modelsim_20or_20questa_115',['Compiling the Simulation with ModelSim or Questa',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md212',1,'']]],
  ['the_20slave_116',['Configuring the slave',['../page_usrp2.html#usrp2_mimocable_cfgslave',1,'']]],
  ['the_20socket_20buffers_117',['Configuring the Socket Buffers',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_netcfg_sockbuff',1,'']]],
  ['the_20software_20tools_20on_20your_20host_20computer_118',['Install and Setup the Software Tools on Your Host Computer',['../page_usrp_b200.html#install_software_tools',1,'']]],
  ['the_20source_20code_119',['Getting the source code',['../page_build_guide.html#build_get_source',1,'']]],
  ['the_20stm32_20microcontroller_120',['The STM32 microcontroller',['../page_usrp_e3xx.html#e320_micro',1,'']]],
  ['the_20subdevice_121',['Specifying the Subdevice',['../page_configuration.html#config_subdev',1,'']]],
  ['the_20subnet_20and_20gateway_122',['Set the subnet and gateway',['../page_usrp2.html#usrp2_altstream_subnet',1,'']]],
  ['the_20top_20level_20makefile_123',['Customizing the top level makefile',['../md_usrp2_2customize__signal__chain.html#autotoc_md104',1,'']]],
  ['the_20uhd_20logging_20facility_124',['The UHD logging facility',['../log_8hpp.html#loghpp_logging',1,'']]],
  ['the_20usrp_125',['Test and Verify the Operation of the USRP',['../page_usrp_b200.html#verify_device_operation',1,'']]],
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  ['the_20usrp_20time_20registers_127',['Method 1 - poll the USRP time registers',['../page_sync.html#sync_time_reg',1,'']]],
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  ['the_20usrp_20x300_20x310_129',['the USRP X300 X310',['../page_usrp_x3x0.html#autotoc_md58',1,'Installing the USRP X300/X310'],['../page_usrp_x3x0.html#autotoc_md64',1,'Installing the USRP X300/X310'],['../page_usrp_x3x0.html#autotoc_md68',1,'Installing the USRP X300/X310']]],
  ['the_20usrp2_20s_20ip_20address_130',['Change the USRP2&apos;s IP address',['../page_usrp2.html#usrp2_network_changeip',1,'']]],
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  ['the_20x4x0_20front_20panel_20gpio_133',['The X4x0 Front Panel GPIO',['../page_x400_gpio_api.html#x4x0gpio_fpanel',1,'']]],
  ['the_20x4x0_20spi_20mode_134',['The x4x0 SPI Mode',['../page_x400_gpio_api.html#x4x0_spi_iface',1,'']]],
  ['the_20zbx_20cpld_135',['Updating the ZBX CPLD',['../page_zbx.html#zbx_updating_cpld',1,'']]],
  ['the_20zynq_20cpu_20fpga_20and_20host_20operating_20system_136',['The Zynq CPU FPGA and host operating system',['../page_usrp_e3xx.html#e310_zynq',1,'The Zynq CPU/FPGA and host operating system'],['../page_usrp_e3xx.html#e320_zynq',1,'The Zynq CPU/FPGA and host operating system']]],
  ['theory_20of_20operation_137',['Theory of Operation',['../page_fbx.html#fbx_too',1,'Theory of Operation'],['../page_usrp_e3xx.html#e3xx_theory_of_ops',1,'Theory of Operation'],['../page_zbx.html#zbx_too',1,'Theory of Operation']]],
  ['there_20so_20many_20different_20compat_20numbers_138',['Why are there so many different compat numbers?',['../page_compat.html#compat_faq_whymany',1,'']]],
  ['this_20class_139',['graph. Data nodes and workers are derived from this class.',['../classuhd_1_1experts_1_1dag__vertex__t.html#autotoc_md253',1,'']]],
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  ['thread_20priority_20scheduling_20with_20uhd_141',['Thread Priority Scheduling with UHD',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_rtprio_thread',1,'']]],
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  ['through_20mpm_20configuration_20files_146',['Device Configuration through MPM configuration files',['../page_configuration.html#config_mpm',1,'']]],
  ['through_20simulations_147',['FPGA: Testing through Simulations',['../page_rdtesting.html#rdtesting_fpga_testbenches',1,'']]],
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  ['through_20vivado_149',['Simulating with ModelSim through Vivado',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md209',1,'']]],
  ['tick_20rate_20and_20sampling_20rate_150',['Master Clock Rate, Tick Rate, and Sampling Rate',['../page_twinrx.html#twinrx_dboards_mcr',1,'']]],
  ['tick_20rate_20tick_5frate_151',['Tick Rate (&lt;span class=&quot;tt&quot;&gt;tick_rate&lt;/span&gt;)',['../page_properties.html#props_special_props_tickrate',1,'']]],
  ['tick_5frate_152',['Tick Rate (&lt;span class=&quot;tt&quot;&gt;tick_rate&lt;/span&gt;)',['../page_properties.html#props_special_props_tickrate',1,'']]],
  ['time_153',['Synchronizing the Device Time',['../page_sync.html#sync_time',1,'']]],
  ['time_154',['time',['../page_general.html#general_tuning_rfsettling',1,'RF front-end settling time'],['../page_gpsdo_x3x0.html#gpsdox_setting_gps_time',1,'Setting Device Time to GPS time']]],
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  ['time_20priority_20scheduling_156',['Real-Time &amp;amp; Priority Scheduling',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_rtprio',1,'']]],
  ['time_20registers_157',['Method 1 - poll the USRP time registers',['../page_sync.html#sync_time_reg',1,'']]],
  ['time_20resolution_158',['Command Time Resolution',['../page_timedcmds.html#timedcmds_res',1,'']]],
  ['time_20scheduling_20in_20your_20application_159',['Real-Time Scheduling in your Application',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_rtprio_app',1,'']]],
  ['time_20synchronization_160',['Time Synchronization',['../page_usrp_e3xx.html#e31x_hw_sync',1,'Clock and Time Synchronization'],['../page_usrp_e3xx.html#e320_hw_sync',1,'Clock and Time Synchronization']]],
  ['time_20to_20gps_20time_161',['Setting Device Time to GPS time',['../page_gpsdo_x3x0.html#gpsdox_setting_gps_time',1,'']]],
  ['timed_162',['Which commands can be timed?',['../page_timedcmds.html#timedcmds_gen_cmds_what',1,'']]],
  ['timed_20command_20advisory_163',['Multiple Timed Command Advisory',['../page_usrp_x3x0.html#x3x0_misc_timed_cmds_lockup',1,'']]],
  ['timed_20commands_164',['Timed Commands',['../page_timedcmds.html#timedcmds_gen_cmds',1,'General Timed Commands'],['../page_timedcmds.html',1,'Timed Commands']]],
  ['timeouts_165',['Timeouts',['../classuhd_1_1rx__streamer.html#stream_rx_timeouts',1,'']]],
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  ['to_20build_20filesystems_167',['Using Docker to build filesystems',['../page_usrp_e3xx.html#e3xx_fsbuild_docker',1,'']]],
  ['to_20establish_20a_20worker_20node_20data_20node_20dependency_168',['to establish a worker node =&amp;gt; data node dependency',['../classuhd_1_1experts_1_1data__writer__t.html#autotoc_md258',1,'']]],
  ['to_20generation_202_20products_169',['Adding DSP logic to Generation 2 products',['../md_usrp2_2customize__signal__chain.html#autotoc_md103',1,'']]],
  ['to_20gps_20time_170',['Setting Device Time to GPS time',['../page_gpsdo_x3x0.html#gpsdox_setting_gps_time',1,'']]],
  ['to_20implement_20the_20resolve_20method_20in_20a_20subclass_171',['is required to implement the &quot;resolve&quot; method in a subclass.',['../classuhd_1_1experts_1_1worker__node__t.html#autotoc_md259',1,'']]],
  ['to_20load_20fpga_20images_172',['to load FPGA images',['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_jtag',1,'Use JTAG to load FPGA images'],['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_pcie',1,'Use PCI Express to load FPGA images']]],
  ['to_20mpm_20architecture_173',['E310 Migration Guide to MPM architecture',['../page_usrp_e3xx.html#e31x_migration',1,'']]],
  ['to_20stdout_174',['Disabling or redirecting prints to stdout',['../page_general.html#general_misc_prints',1,'']]],
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  ['to_20the_20gps_20module_178',['Sending custom commands to the GPS module',['../page_gpsdo_x3x0.html#gpsdox_custom_cmds',1,'']]],
  ['to_20the_20host_20computer_179',['Connect the USRP to the Host Computer',['../page_usrp_b200.html#connect_device',1,'']]],
  ['to_20the_20microcontroller_180',['Connecting to the microcontroller',['../page_usrp_e3xx.html#e320_getting_started_serial_micro',1,'']]],
  ['to_20uhd_204_181',['Converting UHD 3.x calibration data to UHD 4',['../page_calibration.html#calibration_data_csv',1,'']]],
  ['to_20use_20motherboard_20oscillator_182',['RFX - Modify to use motherboard oscillator',['../page_dboards.html#dboards_rfxmod',1,'']]],
  ['to_20use_20the_20extension_20framework_183',['How to use the Extension Framework',['../page_extension.html#extension_howto',1,'']]],
  ['tool_20support_184',['Section 5: Tool Support',['../md_usrp3_2sim_2writing__sim__makefile.html#autotoc_md231',1,'']]],
  ['tool_20unix_185',['Use the card burner tool (UNIX)',['../page_usrp2.html#usrp2_load_cardburner',1,'']]],
  ['tool_20windows_186',['Use the card burner tool (Windows)',['../page_usrp2.html#usrp2_load_cardburnerwin',1,'']]],
  ['tools_187',['Tools',['../page_mpm.html#mpm_debug',1,'Debugging Tools'],['../md_usrp3_2build__instructions.html#autotoc_md112',1,'Download and Install Xilinx Tools'],['../page_mpm.html#mpm_debug_other',1,'MPM Tools'],['../page_rtp.html#vrt_tools',1,'Tools']]],
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  ['top_20level_20makefile_189',['Customizing the top level makefile',['../md_usrp2_2customize__signal__chain.html#autotoc_md104',1,'']]],
  ['top_20level_20simulation_20module_190',['Writing a Top-level Simulation Module',['../md_usrp3_2sim_2writing__sim__top.html',1,'']]],
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  ['transmit_20receive_20registers_20atr_193',['Transmit Receive Registers ATR',['../page_fbx.html#fbx_atr',1,'Auto-Transmit-Receive Registers (ATR)'],['../page_zbx.html#zbx_atr',1,'Auto-Transmit-Receive Registers (ATR)']]],
  ['transport_194',['Data size restrictions in transport',['../page_transport.html#transport_data_size_restrictions',1,'']]],
  ['transport_20libusb_195',['USB Transport (LibUSB)',['../page_transport.html#transport_usb',1,'']]],
  ['transport_20ni_20rio_196',['PCIe Transport (NI-RIO)',['../page_transport.html#transport_pcie',1,'']]],
  ['transport_20notes_197',['Transport Notes',['../page_transport.html',1,'page_devices']]],
  ['transport_20parameters_198',['Transport parameters',['../page_transport.html#transport_udp_params',1,'Transport parameters'],['../page_transport.html#transport_usb_params',1,'Transport parameters'],['../page_transport.html#transport_pcie_params',1,'Transport parameters']]],
  ['transport_20parameters_199',['Overriding transport parameters',['../page_transport.html#transport_param_overrides',1,'']]],
  ['transport_20protocols_200',['Radio Transport Protocols',['../page_rtp.html',1,'page_uhd']]],
  ['transport_20related_20stream_20arguments_201',['Transport-related Stream Arguments',['../page_configuration.html#config_stream_args_transport',1,'']]],
  ['transport_20sockets_202',['UDP Transport (Sockets)',['../page_transport.html#transport_udp',1,'']]],
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  ['troubleshooting_20ethernet_20issues_204',['Troubleshooting Ethernet Issues',['../page_usrp_x3x0_config.html#x3x0cfg_hosthw_troubleshooting_eth',1,'']]],
  ['troubleshooting_20performance_20issues_205',['Troubleshooting Performance Issues',['../page_usrp_x3x0_config.html#x3x0cfg_hosthw_troubleshooting',1,'']]],
  ['tuning_206',['DSP Tuning',['../page_general.html#general_tuning_dsp',1,'']]],
  ['tuning_207',['tuning',['../page_usrp_b200.html#b200_fe_tuning',1,'Frontend tuning'],['../page_usrp_e3xx.html#e31x_dboard_e310_tuning',1,'Frontend tuning'],['../page_general.html#general_tuning_dsp_sign',1,'Sign of DSP frequency on TX vs. RX tuning']]],
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  ['tuning_20notes_209',['Tuning Notes',['../page_general.html#general_tuning',1,'']]],
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  ['tuning_20process_211',['Two-stage tuning process',['../page_general.html#general_tuning_process',1,'']]],
  ['tuning_20the_20receive_20chain_3a_212',['Tuning the receive chain:',['../page_general.html#general_tuning_rxchain',1,'']]],
  ['tutorials_213',['Getting Started with B206mini Tutorials',['../page_usrp_b200.html#getting_started_tutorials',1,'']]],
  ['tvrx_214',['TVRX',['../page_dboards.html#dboards_tvrx',1,'']]],
  ['tvrx2_215',['TVRX2',['../page_dboards.html#dboards_tvrx2',1,'']]],
  ['twinrx_216',['TwinRX',['../page_dboards.html#dboards_twinrx',1,'TwinRX'],['../page_rdtesting.html#rdtesting_phase_rx_X3x0_twinrx',1,'X3x0 with TwinRX']]],
  ['twinrx_20daughterboard_217',['TwinRX Daughterboard',['../page_twinrx.html',1,'page_dboards']]],
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  ['tx_20testing_222',['TX testing',['../page_rdtesting.html#autotoc_md17',1,'']]],
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  ['type_224',['CVITA Stream Type',['../md_usrp3_2sim_2libs__axi.html#autotoc_md167',1,'']]],
  ['type_225',['type',['../page_stream.html#stream_datatypes_cpu',1,'The host/CPU data type'],['../page_stream.html#stream_datatypes_otw',1,'The link-layer data type']]],
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  ['types_227',['Properties on multi-channel blocks and resource types',['../page_properties.html#props_multichan',1,'']]]
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