var searchData=
[
  ['facility_0',['The UHD logging facility',['../log_8hpp.html#loghpp_logging',1,'']]],
  ['family_20motherboard_20slot_20names_1',['Family Motherboard Slot Names',['../page_configuration.html#config_subdev_slotnames',1,'USRP Family Motherboard Slot Names'],['../page_configuration.html#config_subdev_default',1,'USRP Family Motherboard Slot Names']]],
  ['faq_2',['FAQ',['../page_compat.html#compat_faq',1,'']]],
  ['fbx_20daughterboard_3',['FBX Daughterboard',['../page_fbx.html',1,'page_dboards']]],
  ['fbx_20xcvr_20board_4',['FBX XCVR board',['../page_dboards.html#dboards_fbx',1,'']]],
  ['feature_20list_5',['Feature list',['../page_octoclock.html#octoclock_features',1,'']]],
  ['features_6',['Features',['../page_usrp_e3xx.html#e31x_device',1,'E310-specific Features'],['../page_usrp_e3xx.html#e320_neon',1,'E320-specific Features'],['../page_usrp1.html#usrp1_emul',1,'Missing and Emulated Features']]],
  ['features_7',['features',['../page_usrp1.html#usrp1_emul_list',1,'List of emulated features'],['../page_usrp1.html#usrp1_emul_listmissing',1,'List of missing features']]],
  ['features_20list_8',['features list',['../page_usrp1.html#usrp1_features',1,'Comparative features list'],['../page_usrp2.html#usrp2_features',1,'Comparative features list'],['../page_usrp_b100.html#b100_features',1,'Comparative features list'],['../page_usrp_e1x0.html#e1x0_features',1,'Comparative features list'],['../page_usrp_e3xx.html#e3xx_feature_list',1,'Comparative features list'],['../page_usrp_x3x0.html#x3x0_feature_list',1,'Comparative features list']]],
  ['features_20list_20b200_20b210_20b200mini_20b205mini_20b206mini_9',['Comparative features list - B200/B210/B200mini/B205mini/B206mini',['../page_usrp_b200.html#b200_features',1,'']]],
  ['fedora_10',['Fedora',['../page_install.html#install_linux_ourbins_fedora',1,'Fedora'],['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_netcfg_if',1,'Interface Configuration File (Fedora)'],['../md_usrp3_2build__instructions.html#autotoc_md114',1,'Setting up build dependencies on Ubuntu and Fedora'],['../page_build_guide.html#build_dependencies_fedora',1,'Setting up the dependencies on Fedora']]],
  ['file_20fedora_11',['Interface Configuration File (Fedora)',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_netcfg_if',1,'']]],
  ['file_20i_20o_20sim_5ffile_5fio_20svh_12',['File I/O (sim_file_io.svh)',['../md_usrp3_2sim_2libs__general.html#autotoc_md198',1,'']]],
  ['file_20system_13',['file system',['../page_usrp_e3xx.html#e31x_fs',1,'E310/E312/E313 file system'],['../page_usrp_e3xx.html#e320_fs',1,'E320 file system'],['../page_usrp_e3xx.html#e3xx_getting_started_fs_update',1,'Updating the file system']]],
  ['files_14',['Files',['../page_configfiles.html',1,'Configuration Files'],['../page_calibration.html#ignore_cal_file',1,'Ignoring Calibration Files']]],
  ['files_15',['files',['../page_configuration.html#config_mpm',1,'Device Configuration through MPM configuration files'],['../page_configfiles.html#configfiles_format',1,'Format of the configuration files'],['../page_configfiles.html#configfiles_location',1,'Location of configuration files']]],
  ['filesystems_16',['Using Docker to build filesystems',['../page_usrp_e3xx.html#e3xx_fsbuild_docker',1,'']]],
  ['filesystems_20and_20sd_20card_20images_17',['Building custom filesystems and SD card images',['../page_usrp_e3xx.html#e3xx_fsbuild',1,'']]],
  ['filter_20and_20antenna_20switches_18',['Filter and Antenna Switches',['../page_usrp_e3xx.html#e31x_dboard_e310_band_select',1,'Frontend Filter and Antenna Switches'],['../page_usrp_e3xx.html#e31x_dboard_e310_frontend_a_switches',1,'Frontend Side A Filter and Antenna Switches'],['../page_usrp_e3xx.html#e31x_dboard_e310_frontend_b_switches',1,'Frontend Side B Filter and Antenna Switches']]],
  ['find_19',['find',['../page_usrpctl.html#usrpctl_find',1,'']]],
  ['firewall_20',['Configuring the Firewall',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_netcfg_firewall',1,'']]],
  ['firewall_20issues_21',['Firewall Issues',['../page_usrp_x3x0.html#x3x0_comm_issues_firewall',1,'']]],
  ['firewall_20issues_22',['Firewall issues',['../page_usrp2.html#usrp2_commprob_firewall',1,'']]],
  ['firmware_20and_20fpga_20images_23',['Firmware and FPGA Images',['../page_images.html',1,'page_devices']]],
  ['firmware_20builds_24',['firmware builds',['../page_images.html#images_building_fx2',1,'FX2 firmware builds'],['../page_images.html#images_building_zpu',1,'ZPU firmware builds']]],
  ['firmware_20images_25',['Getting the latest firmware images',['../page_octoclock.html#getting_latest',1,'']]],
  ['firmware_20via_20ethernet_26',['Uploading the firmware via Ethernet',['../page_octoclock.html#firmware',1,'']]],
  ['flags_27',['EEPROM flags',['../page_usrp_e3xx.html#e320_eeprom_flags',1,'']]],
  ['flash_28',['Load the Images onto the On-board Flash',['../page_usrp_x3x0.html#x3x0_flash',1,'']]],
  ['flash_20memory_20and_20eeprom_29',['Flash Memory and EEPROM',['../page_zbx.html#zbx_flash',1,'']]],
  ['flash_20usrp_20n_20series_20only_30',['Load the Images onto the On-board Flash (USRP-N Series only)',['../page_usrp2.html#usrp2_loadflash',1,'']]],
  ['flavors_31',['Flavors',['../page_usrp_e3xx.html#e320_fpga_flavours',1,'FPGA Image Flavors'],['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_fpga_flavours',1,'FPGA Image Flavors']]],
  ['flow_20control_32',['Flow Control',['../page_stream.html#stream_remote_rfnoc_fc',1,'']]],
  ['flow_20control_20parameters_33',['Flow control parameters',['../page_transport.html#transport_udp_flow',1,'']]],
  ['for_20arm_20platforms_34',['Compiling for ARM platforms',['../page_build_guide.html#build_instructions_unix_arm',1,'']]],
  ['for_20b200_20series_35',['Build Instructions (Xilinx ISE only, for B200 series)',['../md_usrp3_2build__instructions.html#autotoc_md122',1,'']]],
  ['for_20custom_20drivers_36',['Extending the calibration utility for custom drivers',['../page_power.html#power_usercal_extend',1,'']]],
  ['for_20dealing_20with_20settling_20time_20after_20tuning_20on_20receive_3a_37',['Pseudo-code for dealing with settling time after tuning on receive:',['../page_general.html#general_tuning_waitcode',1,'']]],
  ['for_20dynamically_20loadable_20modules_38',['Support for dynamically loadable modules',['../page_general.html#general_misc_dynamic',1,'']]],
  ['for_20other_20boards_20that_20usrp1_39',['DBSRX - Modifying for other boards that USRP1',['../page_dboards.html#dboards_dbsrxmod',1,'']]],
  ['for_20seconds_40',['Method 2 - query the GPSDO for seconds',['../page_sync.html#sync_time_gpsdo',1,'']]],
  ['for_20the_20e320_41',['Modifying and compiling UHD and MPM for the E320',['../page_usrp_e3xx.html#e3xx_software_dev',1,'']]],
  ['for_20usb_20linux_42',['Setup Udev for USB (Linux)',['../page_transport.html#transport_usb_udev',1,'']]],
  ['for_20usrp_20x_20series_20device_200_3a_43',['Configuration for USRP-X Series device 0:',['../page_usrp_x3x0.html#autotoc_md69',1,'']]],
  ['for_20usrp_20x_20series_20device_201_3a_44',['Configuration for USRP-X Series device 1:',['../page_usrp_x3x0.html#autotoc_md70',1,'']]],
  ['for_20usrp_20x3x0_20series_45',['System Configuration for USRP X3x0 Series',['../page_usrp_x3x0_config.html',1,'page_usrp_x3x0']]],
  ['for_20x_20series_20pcie_20connectivity_46',['NI RIO Kernel Modules for X-Series PCIe Connectivity',['../page_ni_rio_kernel.html',1,'page_usrp_x3x0']]],
  ['format_20of_20binary_20data_47',['Format of binary data',['../classuhd_1_1usrp_1_1cal_1_1database.html#cal_db_blob',1,'']]],
  ['format_20of_20the_20configuration_20files_48',['Format of the configuration files',['../page_configfiles.html#configfiles_format',1,'']]],
  ['format_20specification_49',['Format Specification',['../page_configuration.html#config_stream_args_cpu_format',1,'CPU Data Format Specification'],['../page_configuration.html#config_stream_args_otw_format',1,'Over-the-wire Data Format Specification']]],
  ['format_20strings_50',['Internal format strings',['../page_converters.html#converters_formats_internal',1,'']]],
  ['formats_20and_20converter_20choice_51',['Formats and Converter Choice',['../page_converters.html#converters_formats',1,'']]],
  ['formatting_52',['Log formatting',['../log_8hpp.html#loghpp_formatting',1,'']]],
  ['forwarding_20behavior_53',['Property Propagation and Action Forwarding Behavior',['../classuhd_1_1rfnoc_1_1split__stream__block__control.html#ss_fwd_behavior',1,'']]],
  ['found_54',['Found',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md216',1,'ModelSim Simulation Libraries Not Found'],['../md_usrp3_2sim_2running__testbenches.html#autotoc_md215',1,'ModelSim/Questa Not Found'],['../md_usrp3_2sim_2running__testbenches.html#autotoc_md214',1,'Vivado Not Found']]],
  ['fpga_55',['FPGA',['../page_usrp_e3xx.html#e3xx_getting_started_fpga_update',1,'Updating the FPGA'],['../page_usrp_x3x0.html#x3x0_getting_started_fpga_update',1,'Updating the FPGA']]],
  ['fpga_20and_20host_20operating_20system_56',['FPGA and host operating system',['../page_usrp_e3xx.html#e310_zynq',1,'The Zynq CPU/FPGA and host operating system'],['../page_usrp_e3xx.html#e320_zynq',1,'The Zynq CPU/FPGA and host operating system']]],
  ['fpga_20builds_57',['FPGA builds',['../page_images.html#images_building_altera',1,'Altera FPGA builds'],['../page_images.html#images_building_xilinx',1,'Xilinx FPGA builds']]],
  ['fpga_20designs_20with_20xilinx_20chipscope_58',['FPGA designs with Xilinx Chipscope',['../page_usrp_e3xx.html#e31x_hw_chipscope',1,'Debugging custom FPGA designs with Xilinx Chipscope'],['../page_usrp_x3x0.html#x3x0_hw_chipscope',1,'Debugging custom FPGA designs with Xilinx Chipscope']]],
  ['fpga_20does_20my_20usrp_20have_59',['FPGA does my USRP have',['../md_usrp2_2build__instructions.html#autotoc_md97',1,'What FPGA does my USRP have?'],['../md_usrp3_2build__instructions.html#autotoc_md110',1,'What FPGA does my USRP have?']]],
  ['fpga_20dsp_20verification_60',['FPGA DSP Verification',['../page_rdtesting.html#rdtesting_fpgadspverif',1,'']]],
  ['fpga_20dsp_20verification_3a_20automatic_20test_20procedure_61',['FPGA DSP Verification: Automatic Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_auto',1,'']]],
  ['fpga_20dsp_20verification_3a_20manual_20test_20procedure_62',['FPGA DSP Verification: Manual Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_manual',1,'']]],
  ['fpga_20functional_20verification_63',['FPGA Functional Verification',['../page_rdtesting.html#rdtesting_fpgafuncverif',1,'']]],
  ['fpga_20functional_20verification_3a_20automatic_20test_20procedure_64',['FPGA Functional Verification: Automatic Test Procedure',['../page_rdtesting.html#rdtesting_fpgafuncverif_auto',1,'']]],
  ['fpga_20functional_20verification_3a_20manual_20test_20procedure_65',['FPGA Functional Verification: Manual Test Procedure',['../page_rdtesting.html#rdtesting_fpgafuncverif_manual',1,'']]],
  ['fpga_20image_20flavors_66',['FPGA Image Flavors',['../page_usrp_e3xx.html#e320_fpga_flavours',1,'FPGA Image Flavors'],['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_fpga_flavours',1,'FPGA Image Flavors']]],
  ['fpga_20images_67',['FPGA Images',['../page_images.html',1,'Firmware and FPGA Images'],['../md_fpga.html#autotoc_md91',1,'Pre-built FPGA Images']]],
  ['fpga_20images_68',['FPGA images',['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_jtag',1,'Use JTAG to load FPGA images'],['../page_usrp_x3x0.html#x3x0_load_fpga_imgs_pcie',1,'Use PCI Express to load FPGA images']]],
  ['fpga_20images_20and_20accessing_20user_20settings_69',['Custom FPGA images and accessing user settings',['../page_usrp_b200.html#b200_customfpga',1,'']]],
  ['fpga_20images_20onto_20the_20device_70',['Load FPGA Images onto the Device',['../page_usrp_x3x0.html#x3x0_load_fpga_imgs',1,'']]],
  ['fpga_20manual_71',['FPGA Manual',['../md_fpga.html',1,'index']]],
  ['fpga_20register_20map_72',['E3XX FPGA Register Map',['../page_usrp_e3xx.html#e3xx_regmap',1,'']]],
  ['fpga_3a_20testing_20through_20simulations_73',['FPGA: Testing through Simulations',['../page_rdtesting.html#rdtesting_fpga_testbenches',1,'']]],
  ['framework_74',['Framework',['../page_extension.html#extension_capabilities',1,'Capabilities of the Extension Framework'],['../page_extension.html#extension_howto',1,'How to use the Extension Framework']]],
  ['framework_20documentation_75',['Extension Framework documentation',['../page_extension.html',1,'page_devices']]],
  ['frequency_76',['frequency',['../page_usrp_x3x0.html#x3x0_hw_x3x0_hw_ref10M',1,'Ref Clock (10 MHz or other frequency)'],['../page_power.html#power_tune_owner',1,'Retaining gain or power levels across frequency']]],
  ['frequency_20bands_77',['Frequency Bands',['../page_twinrx.html#twinrx_frequency_bands',1,'']]],
  ['frequency_20on_20tx_20vs_20rx_20tuning_78',['Sign of DSP frequency on TX vs. RX tuning',['../page_general.html#general_tuning_dsp_sign',1,'']]],
  ['from_20source_79',['Compiling UHD from Source',['../page_build_guide.html#autotoc_md86',1,'']]],
  ['from_20source_80',['from source',['../page_build_guide.html',1,'Building and Installing UHD from source'],['../page_install.html#install_win_source',1,'Building from source']]],
  ['from_20this_20class_81',['graph. Data nodes and workers are derived from this class.',['../classuhd_1_1experts_1_1dag__vertex__t.html#autotoc_md253',1,'']]],
  ['from_20uhd_82',['from UHD',['../page_usrp_e3xx.html#e3xx_usage',1,'Using an E3XX USRP from UHD'],['../page_usrp_x3x0.html#x3x0_usage',1,'Using an X3X0 USRP from UHD']]],
  ['front_20and_20rear_20panel_83',['Front and Rear Panel',['../page_usrp_e3xx.html#e320_panels',1,'']]],
  ['front_20end_20others_84',['Align LOs in the front-end (others)',['../page_sync.html#sync_phase_lootherfe',1,'']]],
  ['front_20end_20sbx_20ubx_20obx_85',['Align LOs in the front-end (SBX, UBX, OBX)',['../page_sync.html#sync_phase_lo',1,'']]],
  ['front_20end_20settling_20time_86',['RF front-end settling time',['../page_general.html#general_tuning_rfsettling',1,'']]],
  ['front_20panel_87',['Front Panel',['../page_usrp_e3xx.html#e31x_hw_front_panel',1,'Front Panel'],['../page_usrp_x3x0.html#x3x0_hw_fpanel',1,'Front Panel']]],
  ['front_20panel_20gpio_88',['Front Panel GPIO',['../page_usrp_e3xx.html#e320_gpio',1,'Front Panel GPIO'],['../page_usrp_x3x0.html#x3x0_hw_gpio',1,'Front Panel GPIO'],['../page_usrp_e3xx.html#e3xx_gpio',1,'Internal or Front-Panel GPIO'],['../page_gpio_api.html#xgpio_fpanel',1,'The Front Panel GPIO'],['../page_x400_gpio_api.html#x4x0gpio_fpanel',1,'The X4x0 Front Panel GPIO'],['../page_gpio_api.html#xgpio_fpanel_gpio',1,'X3x0 Front Panel GPIO'],['../page_x400_gpio_api.html#x4x0gpio_fpanel_gpio',1,'X4x0 Front Panel GPIO']]],
  ['front_20panel_20gpio_20connections_89',['Front Panel GPIO Connections',['../page_gpio_api.html#autotoc_md10',1,'Front Panel GPIO Connections'],['../page_usrp_e3xx.html#autotoc_md56',1,'Front Panel GPIO Connections']]],
  ['front_20panel_20leds_90',['Front Panel LEDs',['../page_octoclock.html#front_panel_leds',1,'']]],
  ['front_20panel_20leds_91',['Front panel LEDs',['../page_usrp2.html#usrp2_hw_leds',1,'Front panel LEDs'],['../page_usrp_b100.html#b100_hw_leds',1,'Front panel LEDs'],['../page_usrp_e1x0.html#e1x0_hw_leds',1,'Front panel LEDs']]],
  ['frontend_20bandwidth_92',['Frontend bandwidth',['../page_usrp_b200.html#b200_fe_bw',1,'']]],
  ['frontend_20correction_93',['Device Calibration and Frontend Correction',['../page_calibration.html',1,'page_devices']]],
  ['frontend_20corrections_94',['Frontend Corrections',['../page_calibration.html#calibration_fe_corr',1,'']]],
  ['frontend_20filter_20and_20antenna_20switches_95',['Frontend Filter and Antenna Switches',['../page_usrp_e3xx.html#e31x_dboard_e310_band_select',1,'']]],
  ['frontend_20gain_96',['Frontend gain',['../page_usrp_b200.html#b200_fe_gain',1,'Frontend gain'],['../page_usrp_e3xx.html#e31x_dboard_e310_gain',1,'Frontend gain']]],
  ['frontend_20lo_20lock_20status_97',['Frontend LO lock status',['../page_usrp_e3xx.html#e31x_dboard_e310_pll',1,'']]],
  ['frontend_20names_98',['Daughterboard Frontend Names',['../page_configuration.html#config_subdev_dbnames',1,'']]],
  ['frontend_20notes_99',['RF Frontend Notes',['../page_usrp_b200.html#b200_fe',1,'']]],
  ['frontend_20side_20a_20filter_20and_20antenna_20switches_100',['Frontend Side A Filter and Antenna Switches',['../page_usrp_e3xx.html#e31x_dboard_e310_frontend_a_switches',1,'']]],
  ['frontend_20side_20b_20filter_20and_20antenna_20switches_101',['Frontend Side B Filter and Antenna Switches',['../page_usrp_e3xx.html#e31x_dboard_e310_frontend_b_switches',1,'']]],
  ['frontend_20tuning_102',['Frontend tuning',['../page_usrp_b200.html#b200_fe_tuning',1,'Frontend tuning'],['../page_usrp_e3xx.html#e31x_dboard_e310_tuning',1,'Frontend tuning']]],
  ['functional_20verification_103',['FPGA Functional Verification',['../page_rdtesting.html#rdtesting_fpgafuncverif',1,'']]],
  ['functional_20verification_3a_20automatic_20test_20procedure_104',['FPGA Functional Verification: Automatic Test Procedure',['../page_rdtesting.html#rdtesting_fpgafuncverif_auto',1,'']]],
  ['functional_20verification_3a_20manual_20test_20procedure_105',['FPGA Functional Verification: Manual Test Procedure',['../page_rdtesting.html#rdtesting_fpgafuncverif_manual',1,'']]],
  ['functions_106',['PkgTestExec Tasks and Functions',['../md_usrp3_2sim_2simulation__libraries.html#autotoc_md219',1,'']]],
  ['further_20gps_20sensors_107',['Further GPS sensors',['../page_gpsdo_x3x0.html#gpsdox_sensors',1,'']]],
  ['further_20information_108',['Further Information',['../index.html#autotoc_md12',1,'']]],
  ['fx2_20firmware_20builds_109',['FX2 firmware builds',['../page_images.html#images_building_fx2',1,'']]]
];
