var searchData=
[
  ['valid_5ftypes_0',['VALID_TYPES',['../classuhd_1_1rfnoc_1_1blockdef_1_1arg__t.html#a706fe8fc06101bc2e8983b6a0e820723',1,'uhd::rfnoc::blockdef::arg_t']]],
  ['vals_1',['vals',['../classuhd_1_1dict.html#a2702b2ebdf20b0d2252caeca4bdd73e8',1,'uhd::dict']]],
  ['value_2',['value',['../structuhd_1_1sensor__value__t.html#ab163cb1b4444129eee10caa26df2d953',1,'uhd::sensor_value_t']]],
  ['value_5ferror_3',['value_error',['../structuhd_1_1value__error.html',1,'uhd::value_error'],['../structuhd_1_1value__error.html#a036f8033b9066bc8f86b5eee82db5a81',1,'uhd::value_error::value_error()']]],
  ['value_5ftype_4',['value_type',['../classuhd_1_1rfnoc_1_1property__t.html#a743d843ad019766e2e154f43dace8c19',1,'uhd::rfnoc::property_t']]],
  ['variable_5',['Setup the PATH environment variable',['../page_build_guide.html#path_env',1,'']]],
  ['various_20api_20interfaces_6',['Various API interfaces',['../page_coding.html#coding_api',1,'']]],
  ['vco_7',['VCO',['../page_usrp_b100.html#b100_mcr_vco',1,'Set other rates - uses internal VCO'],['../page_usrp_e1x0.html#e1x0_intvco',1,'Set other rates - uses internal VCO']]],
  ['vcxo_8',['VCXO',['../page_usrp_b100.html#b100_mcr_vcxo',1,'Set 61.44 MHz - uses external VCXO'],['../page_usrp_e1x0.html#e1x0_mcr_extvcxo',1,'Set 61.44MHz - uses external VCXO']]],
  ['vector_5fiir_5fblock_5fcontrol_9',['vector_iir_block_control',['../classuhd_1_1rfnoc_1_1vector__iir__block__control.html',1,'uhd::rfnoc']]],
  ['vector_5fiir_5fblock_5fcontrol_2ehpp_10',['vector_iir_block_control.hpp',['../vector__iir__block__control_8hpp.html',1,'']]],
  ['vector_5fto_5fpybytes_11',['vector_to_pybytes',['../pybind__adaptors_8hpp.html#a81100ecd1659ecf3ff08d73d821c2fa7',1,'pybind_adaptors.hpp']]],
  ['verbosity_12',['verbosity',['../structuhd_1_1log_1_1logging__info.html#ab82d4c1db23d83f1a8a854a928c5f465',1,'uhd::log::logging_info']]],
  ['verification_13',['Verification',['../page_rdtesting.html#rdtesting_fpgadspverif',1,'FPGA DSP Verification'],['../page_rdtesting.html#rdtesting_fpgafuncverif',1,'FPGA Functional Verification']]],
  ['verification_3a_20automatic_20test_20procedure_14',['Verification: Automatic Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_auto',1,'FPGA DSP Verification: Automatic Test Procedure'],['../page_rdtesting.html#rdtesting_fpgafuncverif_auto',1,'FPGA Functional Verification: Automatic Test Procedure']]],
  ['verification_3a_20manual_20test_20procedure_15',['Verification: Manual Test Procedure',['../page_rdtesting.html#rdtesting_fpgadspverif_manual',1,'FPGA DSP Verification: Manual Test Procedure'],['../page_rdtesting.html#rdtesting_fpgafuncverif_manual',1,'FPGA Functional Verification: Manual Test Procedure']]],
  ['verify_20the_20contents_20of_20your_20kit_16',['Verify the Contents of Your Kit',['../page_usrp_b200.html#verify_contents',1,'']]],
  ['verify_20the_20operation_20of_20the_20usrp_17',['Test and Verify the Operation of the USRP',['../page_usrp_b200.html#verify_device_operation',1,'']]],
  ['version_18',['Kernel Version',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_kernel',1,'']]],
  ['version_20of_20the_20compat_20number_20supported_19',['Why is only one version of the compat number supported?',['../page_compat.html#compat_faq_why1',1,'']]],
  ['version_20of_20vivado_20',['Upgrade IP to the environment version of Vivado',['../md_usrp3_2vivado__env__utils.html#autotoc_md247',1,'']]],
  ['version_2eh_21',['version.h',['../version_8h.html',1,'']]],
  ['versioning_22',['UHD Semantic Versioning',['../page_semver.html',1,'page_uhd']]],
  ['vh_23',['vh',['../md_usrp3_2sim_2libs__axi.html#autotoc_md154',1,'AXI4 Stream (sim_axis_lib.vh)'],['../md_usrp3_2sim_2libs__general.html#autotoc_md193',1,'Clocks and Resets (sim_clks_rsts.vh)'],['../md_usrp3_2sim_2libs__axi.html#autotoc_md164',1,'Compressed VITA (sim_chdr_lib.vh)'],['../md_usrp3_2sim_2libs__general.html#autotoc_md186',1,'Execution and Reporting (sim_exec_report.vh)'],['../md_usrp3_2sim_2libs__axi.html#autotoc_md178',1,'Memory Mapped AXI4 (sim_axi4_lib.vh)']]],
  ['via_20command_20line_24',['Device discovery via command line',['../page_identification.html#id_identifying_cmdline',1,'']]],
  ['via_20ethernet_25',['Uploading the firmware via Ethernet',['../page_octoclock.html#firmware',1,'']]],
  ['via_20macports_26',['Via MacPorts',['../page_install.html#install_osx_macports',1,'']]],
  ['via_20name_27',['Discovery via name',['../page_identification.html#id_naming_discovery',1,'']]],
  ['vid_5fpid_5fpair_5ft_28',['vid_pid_pair_t',['../classuhd_1_1transport_1_1usb__device__handle.html#ae52620333fed7cd947c397859900e5f4',1,'uhd::transport::usb_device_handle']]],
  ['visa_20scpi_20based_20devices_29',['VISA/SCPI based devices',['../page_power.html#power_usercal_extend_visa',1,'']]],
  ['visibility_5ft_30',['visibility_t',['../classuhd_1_1soft__regmap__t.html#acd62020ff86f205909f396847bbc51ac',1,'uhd::soft_regmap_t']]],
  ['visual_20studio_31',['Build the project in Visual Studio',['../page_build_guide.html#build_in_msvc',1,'']]],
  ['vita_20sim_5fchdr_5flib_20vh_32',['Compressed VITA (sim_chdr_lib.vh)',['../md_usrp3_2sim_2libs__axi.html#autotoc_md164',1,'']]],
  ['vivado_33',['Vivado',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md209',1,'Simulating with ModelSim through Vivado'],['../md_usrp3_2vivado__env__utils.html#autotoc_md247',1,'Upgrade IP to the environment version of Vivado']]],
  ['vivado_202021_201_34',['Vivado 2021 1',['../md_usrp3_2build__instructions.html#autotoc_md121',1,'Error During cs_server Initialization in Vivado 2021.1'],['../md_usrp3_2build__instructions.html#autotoc_md120',1,'N2rt13HDRTExceptionE in Vivado 2021.1']]],
  ['vivado_20block_20design_20bd_35',['Modify existing Vivado Block Design (BD)',['../md_usrp3_2vivado__env__utils.html#autotoc_md244',1,'']]],
  ['vivado_20environment_20utilities_36',['Vivado Environment Utilities',['../md_usrp3_2vivado__env__utils.html',1,'']]],
  ['vivado_20hardware_20console_37',['Launch Vivado Hardware Console',['../md_usrp3_2vivado__env__utils.html#autotoc_md249',1,'']]],
  ['vivado_20ip_38',['Vivado IP',['../md_usrp3_2vivado__env__utils.html#autotoc_md242',1,'Create Vivado IP'],['../md_usrp3_2vivado__env__utils.html#autotoc_md246',1,'List supported Vivado IP'],['../md_usrp3_2vivado__env__utils.html#autotoc_md243',1,'Modify existing Vivado IP']]],
  ['vivado_20make_20options_39',['Xilinx Vivado Make Options',['../md_usrp3_2build__instructions.html#autotoc_md147',1,'']]],
  ['vivado_20not_20found_40',['Vivado Not Found',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md214',1,'']]],
  ['vivado_20only_41',['Build Instructions (Xilinx Vivado only)',['../md_usrp3_2build__instructions.html#autotoc_md116',1,'']]],
  ['vivado_20tcl_20based_20block_20design_42',['Modify existing Vivado Tcl-based Block Design',['../md_usrp3_2vivado__env__utils.html#autotoc_md245',1,'']]],
  ['vivado_20xsim_43',['Using Xilinx Vivado XSim',['../md_usrp3_2sim_2running__testbenches.html#autotoc_md206',1,'']]],
  ['vivado_5fenv_5futils_2emd_44',['vivado_env_utils.md',['../vivado__env__utils_8md.html',1,'']]],
  ['volatility_45',['Certificate of Volatility',['../page_usrp_b200.html#b200_letter_of_volatility',1,'']]],
  ['volk_46',['Compiling GNURadio with Volk',['../page_usrp_x3x0_config.html#x3x0cfg_hostpc_volk_volk',1,'']]],
  ['voltage_47',['Configuring GPIO Voltage',['../page_x400_gpio_api.html#x4x0_gpio_voltage',1,'']]],
  ['vrt_48',['VRT',['../page_rtp.html#rtp_vrt',1,'']]],
  ['vrt_5fchdr_2edox_49',['vrt_chdr.dox',['../vrt__chdr_8dox.html',1,'']]],
  ['vrt_5fif_5fpacket_2ehpp_50',['vrt_if_packet.hpp',['../vrt__if__packet_8hpp.html',1,'']]],
  ['vs_20embedded_20mode_51',['Network vs. Embedded Mode',['../page_mpm.html#mpm_modes',1,'']]],
  ['vs_20rx_20tuning_52',['Sign of DSP frequency on TX vs. RX tuning',['../page_general.html#general_tuning_dsp_sign',1,'']]]
];
